1. Field of the Invention
The present invention relates to an array substrate and method of fabricating an array substrate, and more particularly, to a thin film transistor array substrate and a method of fabricating a thin film transistor array substrate.
2. Description of the Related Art
In general, liquid crystal display (LCD) devices control light transmittance of liquid crystal material using an induced electric field to display images. The LCD device includes a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate, wherein the light transmittance of the liquid crystal material is controlled by the induced electric field formed between the common electrode and the pixel electrode. The LCD device comprises a thin film transistor (TFT) array substrate (a lower substrate) and a color filter array substrate (an upper substrate) attached together to face each other. In addition, a spacer is provided between the lower and upper substrates to provide a uniform cell gap therebetween, and the liquid crystal material is injected into the cell gap provided by the spacer. The TFT array substrate includes a plurality of signal lines, a plurality of thin film transistors, and an alignment film for providing liquid crystal alignment. The color filter array substrate includes a color filter for producing colored light, a black matrix for preventing light leakage, and an alignment film for providing liquid crystal alignment.
Since fabrication of the TFT array substrate involves semiconductor fabricating processes including a plurality of mask processes, the fabrication process is both complicated and costly. In order to solve this problem, the TFT array substrate has been developed having a reduced number of mask processes. Accordingly, because a single mask process includes individual sub-processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection processes, a four-round mask process has been developed.
FIG. 1 is a plan view of a thin film transistor array substrate according to the related art;
FIG. 1 is a plan view illustrating a related art thin film transistor array substrate using the four-round mask process, and FIG. 2 is a cross sectional view along I-I′ of FIG. 1 according to the related art. In FIGS. 1 and 2, a TFT array substrate comprises a gate line 2 and a data line 4, which have a gate insulating film 46 therebetween, formed to intersect on a lower substrate 45. In addition, a TFT 6 is formed at each intersection of the gate and data lines 2 and 4, a pixel electrode 14 is formed in a pixel region defined by the intersection of the gate and data lines 2 and 4, a storage capacitor 20 is formed at an overlapped portion between the gate line 2 and a storage electrode 22, a gate pad 24 is connected to the gate line 2, and a data pad 30 is connected to the data line 4.
The TFT 6 responds to gate signals transmitted along the gate line 2 such that pixel signals transmitted along the data line 4 are charged to the pixel electrode 14. Accordingly, the TFT 6 comprises a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 14. Furthermore, the TFT 6 includes an active layer 48 overlapping the gate electrode 8 with a gate insulating film 46 positioned between the TFT 6 and the gate electrode 8, thereby defining a channel between the source electrode 10 and the drain electrode 12. In addition, the data line 4, a lower data pad electrode 32, and the storage electrode 22 each overlie the active layer 48, wherein an ohmic contact layer 50 is formed on the active layer 48 for making ohmic contact with the data line 4, and the source electrode 10, the drain electrode 12, the lower data pad electrode 32, and the storage electrode 22 are formed on the ohmic contact layer 50. The pixel electrode 14, which is connected to the drain electrode 12 of the TFT 6 via a first contact hole 13 passing through a passivation film 52, is formed within the pixel region 5.
In FIGS. 1 and 2, an electric field is formed between the pixel electrode 14, which receives the pixel signals via the TFT 6, and a common electrode, which receives reference voltages. Accordingly, liquid crystal molecules of the liquid crystal material (not shown) arranged between the TFT array substrate and the color filter array substrate rotate due to dielectric anisotropy. Thus, the light transmittance within the pixel region 5 differs in accordance with a rotation amount of the liquid crystal molecules, thereby producing images.
In FIG. 2, the storage capacitor 20 consists of a storage electrode 22, which overlaps the gate line 2 with the gate insulating film 46, the active layer 48, and the ohmic contact layer 50 positioned therebetween, and a pixel electrode 14 connected via a second contact hole 21 passing through the storage electrode 22 and the passivation film 52. Accordingly, the storage capacitor 20 allows a pixel signal transmitted to the pixel electrode 14 to be stably maintained until a next pixel signal is transmitted to the pixel electrode 14.
In FIG. 2, the gate pad 24 consists of a gate pad lower electrode 26 extending from the gate line 2, and a gate pad upper electrode 28 connected, via a third contact hole 27 passing through the gate insulating film 46 and the passivation film 52, to the gate pad lower electrode 26. Although not shown, the gate pad 24 is connected to a gate driver and supplies gate signals to the gate line 2.
In FIG. 2, the data pad 30 consists of a lower data pad electrode 32 extending from the data line 4, and an upper data pad electrode 34 connected, via a fourth contact hole 33 passing through the passivation film 52, to the lower data pad electrode 32. Although not shown, the data pad 30 is connected to a data driver and supplies data signals to the data line 2.
FIGS. 3A to 3D are cross sectional views of a method of fabricating the thin film transistor array substrate of FIG. 2 according to the related art. In FIG. 3A, a first conductive pattern group including the gate line 2, the gate electrode 8, and the gate pad lower electrode 26 is formed on the lower substrate 45 using a first mask process. For example, a gate metal layer is formed on the upper substrate 45 by a deposition technique, such as sputtering, to form a double gate metal layer including aluminum. Then, the gate metal layer is patterned by photolithographic and etching processes using a first mask to form the first conductive pattern group including the gate line 2, the gate electrode 8, and the gate pad lower electrode 26.
In FIG. 3B, the gate insulating film 46 is formed on the lower substrate 45 provided with the first conductive pattern group. Then, a semiconductor pattern group including the active layer 48 and the ohmic contact layer 50 and a second conductive pattern group including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32, and the storage electrode 22 are formed on the gate insulating film 46 using a second mask process. For example, the gate insulating film 46, an amorphous silicon layer, a n+ amorphous silicon layer, and a source/drain metal layer are sequentially formed on the lower substrate 45 provided with the first conductive pattern group by deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD) and-sputtering. The gate insulating film 46 is made of an inorganic insulating material, such as silicon oxide (SiOx) or silicon nitride (SiNx), and the source/drain metal layer is made of a molybdenum (Mo), a titanium (Ti), tantalum (Ta), or a molybdenum alloy.
Then, a photo-resist pattern is formed on the source/drain metal layer by photolithographic processes using a second mask. Accordingly, a diffractive exposure mask having a diffractive exposure portion corresponding to a channel region of the TFT is used as a second mask. Thus, a photo-resist pattern of the channel portion has a lower height than other photo-resist patterns corresponding to other regions. Subsequently, the source/drain metal layer is patterned by a wet etching process using the other photo-resist patterns to provide a second conductive pattern group including the data line 4, the source electrode 10, the drain electrode 12, which is integral to the source electrode 10, and the storage electrode 22. Next, the amorphous silicon layer and the n+ amorphous silicon layer are simultaneously patterned by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer 50 and the active layer 48.
Then, relatively low height portions of the photo-resist pattern are removed from the channel region by an ashing process, and the source electrode, the source/drain metal pattern, and the ohmic contact layer 50 of the channel region are etched using the dry etching process. Thus, the active layer 48 of the channel region is exposed to electrically separate the source electrode 10 from the drain electrode 12. Next, remaining portions of the photo-resist pattern on the second conductive pattern group are removed using a stripping process.
In FIG. 3C, the passivation film 52 including first, second, third, and fourth contact holes 13, 21, 27, and 33 are formed on the gate insulating film 46 provided with the second conductive pattern group using a third mask process. For example, the passivation film 52 is entirely formed on the gate insulating film 46 provided with the second conductive pattern group by a deposition technique, such as PECVD. Then, the passivation film 52 is patterned by photolithographic and etching processes using the third mask to form the first, second, third, and fourth contact holes 13, 21, 27, and 33. The first contact hole 13 is formed to pass through the passivation film 52 and expose a portion of the drain electrode 12, and the second contact hole 21 is formed to pass through the passivation film 52 and expose a portion of the storage electrode 22. The third contact hole 27 is formed to pass through the passivation film 52 and the gate insulating film 46 and expose a portion of the gate pad lower electrode 26, and the fourth contact hole 33 is formed to pass through the passsivation film 52 and expose a portion of the lower data pad electrode 32. When a metal having a high ratio of dry etching, such as molybdenum (Mo), is used for the source/drain metal, the first contact hole 13, the second contact hole 21, and the fourth contact hole 33 are formed to pass through to the exposed portions of the drain electrode 12, the storage electrode 22, and the lower data pad electrode 32, respectively. In addition, the passivaion film 52 is made of an inorganic insulating material, such as the gate insulating film 46, or made of an organic insulating material having a small dielectric constant, such as an acrylic organic compound, benzocyclobutene (BCB) or perfluorocyclobutane (PFCB).
In FIG. 3D, a third conductive pattern group including the pixel electrode 14, the gate pad upper electrode 28, and the upper data pad electrode 34 is formed on the passivation film 52 using a fourth mask process. For example, a transparent conductive film is coated onto the passivation film 52 by a deposition technique, such as sputtering, and is patterned by photolithographic and etching processes using a fourth mask. The transparent conductive film may be made of indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO), or indium-tin-zinc-oxide (ITZO). Accordingly, the third conductive pattern group includes the pixel electrode 14, the gate pad upper electrode 28, and the upper data pad electrode 34. The pixel electrode 14 has a first end electrically connected to the drain electrode 12 through the first contact hole 13, and a second end electrically connected to the storage electrode 22 through the second contact hole 21. In addition, the gate pad upper electrode 28 is electrically connected to the gate pad lower electrode 26 through the third contact hole 27, and the upper data pad electrode 34 is electrically connected to the lower data pad electrode 32 through the fourth contact hole 33.
However, as described above, the TFT array substrate and method of fabricating the TFT array substrate includes a four-round mask process that includes complex, individual fabrication processes having relatively high production costs.